TSMC 2026Q1 results

TSMC reported exceptionally strong financial results for the first quarter of 2026 on April 16, 2026. All key financial metrics exceeded both market expectations and the company’s own guidance, primarily driven by the explosion in AI demand and its leadership in advanced semiconductor nodes.

Financial Performance Highlights

In 2026Q1, consolidated revenue reached NT$1,134.10B (approximately US$35.90B), representing a 35.1% increase year-over-year and an 8.4% increase from the previous quarter. Net income for the quarter was NT$572.48B, with earnings per share (EPS) of NT$22.08, marking a 58.3% increase compared to the same period last year. Profitability was a standout feature, with the gross margin reaching 66.2% (up 3.9 percentage points from the previous quarter) and the operating margin climbing to 58.1%.

Key Business Drivers

Record-Breaking ProfitabilityThe gross and operating margins significantly surpassed the high end of previous guidance. This success was attributed to higher capacity utilization, ongoing cost-cutting initiatives, and favorable foreign exchange rates. A net profit margin of 50.5% underscores the company’s efficiency in converting massive revenue growth into bottom-line profit.
Dominance of Advanced ProcessesAdvanced technologies (7nm and below) accounted for 74% of total wafer revenue, solidifying TSMC’s grip on the high-end market. Specifically, 5nm (N5) remained the largest contributor at 36% of revenue. 3nm (N3) saw its share rise to 25% as production continued to scale rapidly, while 7nm (N7) contributed 13%.
HPC and AI as Growth EnginesStrong demand for AI servers and High-Performance Computing (HPC) served as the primary growth engine. The HPC segment grew by 20% this quarter and now represents 61% of total revenue, effectively offsetting seasonal fluctuations in the consumer electronics sector.

Future Outlook and Capital Allocation

Q2 Guidance: Revenue is expected to fall between US$39.0B and US$40.2B, indicating a sequential growth of approximately 10%.
Full-Year Forecast: Management has revised its 2026 full-year USD revenue growth outlook upward to more than 30%.
Capital Expenditure: The budget remains between US$520B and US$560B, with a preference toward the higher end to support 2nm development and the expansion of CoWoS advanced packaging capacity.

In the 2026Q1 earnings call, TSMC revealed several critical strategic and structural shifts that indicate the semiconductor industry is entering a new cycle dominated by AI:

1. The Official Launch of the 2nm (N2) Era

The most significant technical milestone this quarter was the official start of volume production for 2nm process technology in January 2026 at the Baoshan (Fab 20) and Kaohsiung (Fab 22) facilities. This transition represents a fundamental shift from FinFET to Gate-All-Around (GAA) nanosheet architecture. Initial reports suggest that despite the extreme technical complexity, starting yields have reached a healthy level of 65%-80%.

2. AI Demand Evolution: From Single Points to “Agentic AI”

Management noted that AI demand has expanded beyond pure GPUs to include CPUs and Power Management ICs (PMIC). Due to the rise of the “Agentic AI” trend, TSMC has revised its long-term Compound Annual Growth Rate (CAGR) forecast for AI accelerators upward from 50% to 56%-59%, indicating that the AI demand lifecycle is longer and more resilient than previously anticipated.

3. A “New Normal” in Profitability Structure

TSMC’s gross margin surged to 66.2% this quarter, an exceptionally rare figure in the semiconductor manufacturing industry. This reflects immense pricing power; reports suggest that 2nm wafer prices have surpassed US$30,000 per wafer. Management expressed confidence in maintaining a long-term gross margin of 53% or higher, even as overseas expansion in the US, Japan, and Germany introduces a 2%-3% margin dilution, which they intend to offset through price adjustments and process optimization.

4. Capital Expenditure Trending Toward the High End

The company narrowed its 2026 capital expenditure guidance toward the “high end” of the US$52B to US$56B range. This reflects an accelerated expansion phase, specifically to address the severe supply-demand gap for CoWoS advanced packaging capacity and to prepare for the massive ramp-up of 2nm production.

5. Structural Shift in Revenue Composition

The High-Performance Computing (HPC) platform now accounts for 61% of total revenue, growing 20% sequentially and solidifying its position as the company’s primary pillar. In contrast, Smartphone revenue declined by 11% this quarter, shrinking to a 26% share. This marks a formal transition for TSMC into a company driven by “computing power” rather than “mobile communication.”

Based on the April 2026 earnings call, TSMC maintains an highly optimistic outlook for the second quarter (2026Q2) and the remainder of the year. The primary growth engines are concentrated in these four core areas:

1. Full-Scale Ramp-up of 2nm (N2) Process

Following the official start of volume production in 2026Q1, the second quarter marks the beginning of a significant capacity ramp-up phase.

Capacity Expansion: Monthly capacity for 2nm is projected to double from 40k wafers at the end of 2025 to between 80k and 100k wafers by the end of 2026.
Customer Adoption: Management confirmed that customer engagement for 2nm in its early stages is faster than any previous node (including 3nm and 5nm), which will contribute significant unit price premiums to revenue starting in Q2.

2. Breakthrough in Advanced Packaging (CoWoS) Capacity

CoWoS capacity has long been a bottleneck for AI chip shipments, but a major supply release is expected in 2026Q2.

Aggressive Expansion: TSMC plans to expand CoWoS monthly capacity from 70k wafers at the end of 2025 to 115k wafers within 2026. The second quarter is a critical window for this new capacity to come online.
Technology Mix: Beyond traditional CoWoS, revenue contributions from CoWoS-L and SoIC technologies are increasing, which is vital for supporting the next-generation AI chips from Nvidia, AMD, and major hyperscalers’ custom ASIC projects.

3. Structural Demand for AI and HPC

The nature of AI demand is evolving from early model training toward Agentic AI and Edge AI applications.

Upward Revision: Citing “insatiable” demand for AI infrastructure, TSMC raised its 2026 full-year USD revenue growth guidance to over 30%.
HPC Dominance: HPC revenue is expected to maintain its share above 60% in Q2, serving as a powerful buffer against the slower recovery in consumer electronics (smartphones and PCs).

4. Average Selling Price (ASP) and Pricing Strategy

Due to the extreme tightness in 3nm and 2nm capacity, TSMC has demonstrated formidable bargaining power.

Price Adjustments: Market reports indicate that TSMC has implemented price increases of 3% to 5% for 3nm and 5nm nodes. The benefits of these adjustments will be more visibly reflected in the Q2 gross margins.
Margin Outlook: The company estimates that the gross margin for Q2 could further challenge new highs in the range of 65.5% to 67.5%.

2026Q2 Financial Guidance

Revenue Forecast: US$39.0M to US$40.2M (approximately 10% sequential growth and 32% year-over-year growth).
Capital Expenditure: Trending toward the high end of the US$52B to US$56B range, signaling high confidence in future demand.

Based on the latest earnings call in April 2026 and consensus analyst forecasts, TSMC’s EPS is expected to enter a period of aggressive expansion over the next year, fueled by unrelenting AI demand, the 2nm ramp-up, and significant pricing power.

EPS Growth Projections

Based on current market consensus and management guidance:

2026 Full-Year Forecast: Analysts widely expect full-year EPS to land between NT$88 and NT$95 (approximately US$14.50 to US$15.50 per ADR). Compared to 2025, this represents an annual growth of roughly 41% to 45%.
2027 Preliminary Outlook: As 2nm capacity reaches full scale, EPS for 2027 is projected to climb further, potentially exceeding NT$110 (approximately US$19.17 per ADR).

Key Drivers for EPS Momentum

Structural Margin ExpansionTSMC achieved a staggering 66.2% gross margin in 2026Q1, with Q2 guidance remaining high at 65.5%–67.5%. This profitability, well above the historical average of 53%, sets a higher baseline for earnings. Price hikes and a larger mix of advanced nodes are expected to offset cost pressures from overseas expansions.
Premium Contribution from 2nm (N2)The 2nm process began volume production in early 2026. Due to the complexity of the Nanosheet architecture, wafer prices are reported to have surpassed US$30,000. As capacity ramps up through the second half of the year, these high-margin products will significantly lift the Average Selling Price (ASP), directly boosting EPS.
Dominance of High-Margin AI RevenueThe HPC (High-Performance Computing) segment now accounts for 61% of revenue. Management has revised the CAGR for AI-related revenue upward to over 50%. The high-margin nature of AI chips makes TSMC’s earnings profile more resilient and less dependent on the cyclical nature of the smartphone market.
Full Capacity and Pricing PowerAdvanced process capacity is expected to remain fully booked through 2028. In this supply-constrained environment, TSMC has implemented price increases of 5%–10% for 3nm and 5nm nodes. The full impact of these adjustments will materialize in the financial statements during the latter half of 2026 and into 2027.

Potential Risks to Monitor

Despite the bullish EPS outlook, several variables remain:

Overseas Operational Costs: Higher costs at US and German fabs could lead to a 2%–3% margin dilution in the long run.
Geopolitical Factors: Supply chain stability and changes in export control policies.
Utility and Tax Impacts: Rising electricity rates in Taiwan and global minimum tax adjustments may slightly impact net profit margins.

Nanosheet technology represents a fundamental shift in semiconductor manufacturing. It is the core transistor architecture utilized by TSMC for its 2nm (N2) process, marking a departure from the long-standing FinFET design.

1. What is a Nanosheet?

A nanosheet is a type of Gate-All-Around (GAA) transistor. In the previous FinFET (Fin Field-Effect Transistor) structure, the gate wraps around the channel on three sides. In a nanosheet structure, the gate completely surrounds the channel on all four sides. The channel itself consists of several thin, horizontally stacked sheets of silicon.

2. Why the Shift from FinFET?

As process nodes shrink below 3nm, FinFETs encounter physical limitations that nanosheets are designed to solve:

Superior Leakage Control: In ultra-small transistors, the gate often struggles to fully “turn off” the channel, leading to power leakage and heat. Because the nanosheet gate surrounds the channel entirely, it provides much tighter electrostatic control, significantly reducing leakage.
Higher Drive Current: By stacking multiple sheets vertically, nanosheets increase the “effective width” of the channel within the same footprint, allowing more current to flow and improving performance.
Design Flexibility: Nanosheet widths can be varied during the design phase. Engineers can use wider sheets for high performance or narrower sheets to prioritize power efficiency, a level of customization not possible with the fixed-height “fins” of FinFETs.

3. Core Advantages of TSMC 2nm Nanosheets

According to TSMC’s technical specifications for the N2 node, the transition to nanosheet technology provides:

Increased Speed: Roughly 10%–15% faster performance at the same power level compared to the 3nm (N3E) process.
Reduced Power Consumption: Approximately 25%–30% lower power usage at the same speed.
Higher Density: A chip density increase of over 1.1x, allowing for more transistors to be packed into the same physical area.

4. Technical Challenges

Moving to nanosheets is a high-stakes engineering feat. It requires:

Complex Epitaxy and Etching: Manufacturers must grow alternating layers of Silicon (Si) and Silicon-Germanium (SiGe), then selectively etch away the SiGe to leave “suspended” silicon sheets.
Yield Management: TSMC reported in its 2026Q1 earnings that the initial 2nm yield is between 65%–80%, which is considered very healthy for the debut of a brand-new architecture.

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